The present invention relates to the deposition of dielectric layers during semiconductor substrate processing. More specifically, the present invention relates to a method and apparatus for forming halogen-doped layers having a low dielectric constant and high film stability. The process of the present invention may also be applied to the formation of silicon oxide, silicon nitride and other types of layers.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (CVD). Thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage metal layers on device structures.
Plasma enhanced CVD (PECVD) processes, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate to the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place and thus lowers the required temperature for such CVD processes. The relatively low temperature used in CVD processes makes them suitable for the formation of insulating layers over deposited metal or polysilicon layers. A common material used in such insulating layers (also referred to as dielectric layers) is silicon oxide. Silicon oxide films are well suited for use as dielectric layers because of their electrical and physical properties.
Semiconductor device geometries have decreased dramatically in size since such devices were first introduced several decades ago. During that time, integrated circuits have generally followed the two year/half-size rule (often called "Moore's Law"), meaning that the number of devices which will fit on a chip doubles every two years. Today's semiconductor fabrication plants routinely produce devices with feature sizes of 0.5 microns or even 0.35 microns, and tomorrow's plants will be producing devices with even smaller feature sizes.
As feature sizes become smaller, maintaining certain values of film characteristics, such as the dielectric constant of insulating layers, becomes critical. The advent of multilevel metal technology, employing three, four, or more metallic layers, has spurred interest in lowering the dielectric constant of insulating layers such as intermetal dielectric layers (IMD) deposited by PECVD methods. Low dielectric constant films are particularly desirable for IMI layers to reduce the RC time-delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine into a silicon oxide layer. An example of halogen incorporation is described in U.S. Ser. No. 08/344,283 commonly assigned to Applied Materials, Inc. filed on Nov. 24, 1994 and incorporated herein by reference. Fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network. Fluorine-doped silicon oxide films are also referred to as fluoro-silicate glass (FSG) films.
In addition to decreasing the dielectric constant, incorporating fluorine in intermetal silicon oxide layers also helps solve common problems encountered in fabricating smaller geometry devices, such as filling closely spaced gaps in semiconductor structures. Because fluorine is an etching species, it is believed that fluorine doping introduces an etching effect on the growing film. This simultaneous deposition/etching effect allows FSG films to have improved gap filling capabilities such that the films are able to adequately cover adjacent metal layers having an aspect ratio of 1.8 or more.
Thus, manufacturers desire to include fluorine in various dielectric layers and particularly in intermetal dielectric layers. A problem with the incorporation of fluorine in silicon oxide or similar films, however, has been keeping the fluorine in the film. Experiments have shown only a certain level of fluorine is retained in a silicon oxide layer, even when the gas flow of the fluorine containing source gas is increased during the CVD process.
At least two separate forces affect the fluorine retention rate. The first is that FSG films absorb moisture easily. Clean room ambients may include airborne moisture, as may some processing steps performed during substrate processing. When a substrate is exposed to the ambient in a clean room, for example, during transfer to a new processing chamber after oxide layer deposition, the FSG layer may absorb moisture, thereby increasing the film's dielectric constant. Absorbed moisture (H.sub.2 O) reacts with the fluorine to form hydrofluoric acid (HF), which attacks the metal films often used as device interconnects in such microelectronic circuits.
Another difficulty encountered with FSG films occurs when the film is exposed to a thermal process such as an anneal process. The high temperature of the thermal processes can move the fluorine atoms out of the oxide layer through metal or other subsequently deposited layers. The excursion of fluorine atoms in this manner is referred to as "outgassing".
Sealing layers have been shown to stabilize halogen-doped films. A sealing layer may consist of a material such as a silicate glass (e.g., undoped silicate glass (USG)). This type of sealing layer is disclosed, for example, in U.S. patent application Ser. No. 08/548,391 entitled "Method and Apparatus for Improving Film Stability of Halogen-Doped Silicon Oxide Films," by P. Lee, S. Robles, A. Gupta, V. S. Rana and A. Verma, filed Oct. 26, 1995, the disclosure of which is incorporated herein by reference. These sealing layers are generally effective in preventing the absorption of water and the outgassing of fluorine during subsequent processing steps.
However, such films may not be ideal for all applications. Certain processing steps used in some fabrication sequences may compromise the characteristics of such films. For example, chemical-mechanical polishing (CMP) operations are sometimes performed on intermediary layers (e.g., IMD layers) in preparation for the deposition of overlying layers. CMT is performed to provide a smooth, flat surface on which these subsequent layers may be formed. In doing so, the CMP step erodes the film being polished. Thus, CMP operations may remove all or part of the sealing layer. Also, regions of a fluorine-doped film may be exposed when the film is etched to allow layer(s) above the film to contact layer(s) below the film. This occurs, for example, when a via is etched leaving the via's sidewalls are exposed until covered during subsequent processing. Fluorine outgassing and moisture absorption can occur through the exposed sidewalls.
From the above, it can be seen that an oxide film having a low dielectric constant is necessary to keep pace with emerging technologies. Furthermore, it can be seen that improved methods of preventing or reducing moisture absorption and outgassing in fluorine-doped oxide films are desirable.